This website is no longer maintained. Its content may be obsolete. Please visit http://home.cern for current CERN information.
Meeting no.2 : Friday 16-02-2000 - reported by Thijs Wijnands & Mike Lamont
Present : M. Jonker, Q.King, A. Butterworth, T.Wijnands, P. Ribeiro, M. Lamont, P. Anderssen.
MJ commented that he had not, in fact, given a presentation on logical architecture in the last meeting. In one of the next meetings, MJ will give his presentation on the logical architecture which is required to allow the implementation of a well designed, flexible, global, integrated system (see also below)
ML detailed this issue by giving a list of expected latencies between subsequent feedback iterations. See table below:
|
Acquisition
|
10 ms
|
20 ms for acquisition - take midpoint (e.g. 1024 turns)
|
|
Network
|
5 ms
|
|
|
Collection of data
|
5 ms
|
|
|
Algorithm
|
10 ms
|
e.g. calculation of orbit correction
|
|
Broadcast to gateways
|
5 ms
|
corrections...
|
|
Transport over FIP
|
0 - 10 ms
|
|
|
Power converter
|
10 ms
|
RST algorithm
|
|
Magnet response
|
10 ms
|
Field penetration - dI/dt. Expected perturbation during
snapback to checked against available voltage.
|
Issues mentioned included: clipping because of saturation of correctors (the dangers of one out of a set for example), and the problem of hysterisis in the corrector magnets.
There was some discussion on the latency induced by the data transport over the FIP - can we eliminate/reduce it ?
QK commented that it is more likely to be 3 +/- 10 ms for the latency. In any case, we can construct it such that the latency is constant.
The magnet response is the dominant factor in the response time of the system. ML showed the slides from Freddy Bordry on which he calculated the maximum ramp rate for the tuning quads, the sextupole and decapole spool pieces. Due to the lower self inductance, the ramp rate in these elements is of the order of 10-40 kA/s which largely sufficient for feedback purposes we are talking about. The situation for the orbit correctors is different - they have a much larger self (7 H) and we should distinguish between small and large kicks if we want to deduce the closed loop bandwidth of the system power converter and magnet.
TW mentioned that the picture is not complete :
10 Hz sampling -> 1 Hz closed loop -> max latency 1/10*fc = 100 ms. Correcting the orbit at a closed loop frequency of 1 Hz means that you will have a gain (error reduction) of 2 at 0.5 Hz, a gain of 10 at 0.1 Hz and so on. This was what was done some 2 years ago. But there is more. The total gain factor D is composed of a dynamic part (Dd) and a static part (Ds) and D=1/(1/Dd +1/Ds). The static part comes from your MICADO algorithm and is limited by the precision and the number of BPMs. The dynamic gain comes from your feedback system and is limited by the phase delay and the sampling rate. The maximum Dd that can be achieved for the orbit is given by the system "PC and magnet". This system has a closed bandwidth of 2 mHz for large kicks (80 % of maximum kick strength) and 1 Hz for small kicks (0.15 % of maximum kick strength).
AB remarked that the orbit correction algorithm should scale the kick strength so as to assure a reasonable closed loop bandwidth.
QK : The PC have a build in limit on dI/dt !
MJ commented that this is dangerous since all power converters should act in a coherent way. If one PC decides to slow down the dI/dt, we will introduce artificial orbit distortions. It was decided that this "nonlinear" area should be avoided at any time.
QK brought up the question of how many UDP packets can be send at the same time to a central machine.
PA replied that this an issue for the front ends, not for the networking. We could investigate the a shared memory system with 3 processors.
It is clear that we need to clearify the issue of a logical architecture. Once this is done, we can proceed with the physical architecture. SPS prototyping with ATM could be interesting in order to get experience. However, no one assumes that this technology is to be used in the LHC. An IP structure definitely needs a special development for the front ends - an example is the work done for ATLAS were they stripped off the TCP/IP stack and used "raw" ethernet with gigabit technology. The present proposal from IT is to put all traffic over a single gigabit network. If this solution is not suitable, we should ask for a "private" network. This means that we need reserve dedicated fibers rather quickly since the CERN policy now is that there will no more multiplexing of links over a single fiber such as we did in the old days with TDM.
It was concluded that we should move on rather rapidly to the discussion on the logical architecture.